1. Field of the Invention
The present invention relates generally to semiconductor device. More particularly, the invention relates to a semiconductor device having a structure of a vertical Field-Effect Transistor (FET), such as a vertical Metal-Oxide-Semiconductor FET (MOSFET), and a method of fabricating the device.
2. Description of the Related Art
Typically, vertical MOSFET structures have been used for power MOSFETs and Insulated-Gate Bipolar Transistors (IGBTs). In particular, if the drain-to-source withstand voltage of power MOSFETs is approximately 10 V to 60 V, power MOSFETs with their gate electrodes in a trench or trenches have been becoming the mainstream.
FIG. 1A is a schematic, partial plan view of a prior-art semiconductor device of this type and FIG. 1B is a schematic, partial cross-sectional view along the line IBxe2x80x94IB in FIG. 1A.
The prior-art semiconductor device of FIGS. 1A and 1B comprises a n+-type semiconductor substrate 111 on which a plurality of vertical MOSFETs 131 are formed. A nxe2x88x92-type epitaxial layer 112 is formed on the substrate 111 to cover its whole surface. The layer 112 serves as the common drain region for the MOSFETs 131 along with the substrate 111.
In the surface area of the epitaxial layer 112, a field dielectric 118 is selectively formed to define approximately rectangular active regions 132 on the substrate 111. In each of the region 132s, a p-type diffusion layer 116 is formed in the surface area of the layer 112. A lattice-shaped trench 113 is formed in the epitaxial layer 116 to penetrate vertically through the same, thereby forming device-formation regions on the substrate 111. Thus, the diffusion layer 116 is divided into rectangular islands by the trench 113, where the islands are arranged at specific intervals over the entire substrate 111. Each of the islands constitutes a base region 116a. The trench 113 extends laterally toward the field dielectric 118. The ends 113a of the trench 113 are located near the isolation dielectric 118.
In the surface area of each base region 116a, n+-type diffusion regions 117 are formed to serve as source regions. Each of the source regions 117 has a frame-like plan shape running along the periphery of the corresponding base region 116a at a specified width.
Gate electrodes 115, which are connected together, are formed in the trench 113 by way of corresponding gate dielectrics 114. The gate dielectrics 114, which are united together, cover the whole inner surface of the trench 113 and are located on the surface of the diffusion layer 116 outside the trench 113. The gate electrodes 115 fill almost all the trench 113 while the tops of the electrodes 115 are exposed from the trench 113.
A gate connection portion 115a having a specific pattern is formed to connect to the gate electrodes 115. The portion 115a is located outside the trench 113. Almost all the portion 115a is placed on the field dielectric 112.
An interlayer dielectric layer 122 is formed on the p-type diffusion layer 116 to cover the gate electrodes 115 and the n+-type source regions 117. The layer 122 has contact holes 120 and a contact hole 121. The holes 120 are located over the respective base regions 116a to expose the corresponding base regions 116a and the corresponding source regions 117. The hole 121 is located over the field dielectric 118 to expose the gate connection portion 115a. 
On the interlayer dielectric layer 122, a source wiring layer 123 and a gate wiring layer 124 are formed. The source wiring layer 123, which covers almost all the active region 132, is mechanically and electrically connected to the base regions 116a and the source regions 117 by way of the contact holes 120. The gate wiring layer 124, which extends along the edge of the active region 132 over the field dielectric 118, is mechanically and electrically connected to the gate connection portion 115a by way of the contact hole 121.
The common drain region (which is formed by the combination of the substrate 111 and the epitaxial layer 112), the source electrodes 117, the gate dielectrics 114, and the gate electrodes 115 constitute the vertical MOSFETs 131 connected in parallel on the substrate 111.
P-n junctions are formed at the interfaces of the epitaxial layer 112 and the base regions 116a (i.e., the diffusion layer 116) The layer 112 serves as an electric-field relaxation layer for relaxing the electric field applied to these p-n junctions, in addition to the function of the common drain region.
With the prior-art semiconductor device 100, as explained above, the gate connection portion 115a formed on the field dielectric 118 outside the trench 113 is connected to the gate wiring layer 124. This connection structure is based on the following reason.
Specifically, the gate electrodes 115 are formed by filling the trench 113 with a conductive material (e.g., n-type polysilicon) using a CVD (Chemical Vapor Deposition) method or the like. Thus, in order to suppress the required thickness of the conductive material for filling the trench 113, the width of the trench 113 needs to be as much as approximately 1.0 xcexcm or less. Moreover, the width of the trench 113 needs to be approximately uniform over the whole length of the trench 113,
Therefore, if the gate wiring layer 124 is directly connected to the gate electrodes 115, the size of the contact holes for electrically connecting the gate wiring layer 124 to the gate electrodes 115 will be as small as approximately 0.6 xcexcm or less while taking the alignment margin in consideration. Since the gate wiring layer 124 is typically formed by sputtering or evaporating a metal such as aluminum (Al), the layer 124 will not be formed to fill such the small contact holes. This means that electrical connection of the layer 124 to the gate electrodes 115 is not realized. For this reason, the gate connection portion 115a is additionally provided outside the trench 113 for this purpose.
The prior-art device 100 has the following problem, because the gate connection portion 115a is located over the ends 113a of the trench 113
As shown in FIG. 1B, the p-type diffusion layer 116 has approximately right-angled top corners 116b at the ends 113a of the trench 113. Thus, the thickness of the gate dielectric 114 near the top corners 116b will be thinner than that on other flat surfaces such as the bottom faces of the trench 113. Furthermore, with the vertical MOSFET of this type, the gate dielectrics 14 are typically formed by a thin silicon dioxide (SiO2) layer with a thickness of approximately 10 to 100 nm generated by thermal oxidation.
Accordingly, if a voltage is applied across the p-type diffusion layer 116 and the gate connection portion 115a, dielectric breakdown of the gate dielectric 114 is likely to occur near the top corners 116b of the layer 116. Thus, a problem that the gate withstand voltage of the MOSFET 131 is insufficient will arise.
This problem can be solved to some extent if a proper heat treatment such as wet oxidation at 1100xc2x0 C. or higher is applied. This is because the corners 116b of the diffusion layer 116 are rounded due to high-temperature wet oxidation. However, high-temperature treatment will cause another problem that high-speed operation of the MOSFET 131 is difficult to be realized as desired. The reason of this problem is that high-temperature treatment makes it difficult for the MOSFET 131 to have a shallow structure, thereby restraining the reduction of the parasitic capacitance.
Accordingly, an object of the present invention is to provide a semiconductor device that raises or improves the gate withstand voltage of a vertical FET, and a method of fabricating the device.
Another object of the present invention is to provide a semiconductor device that makes it possible to raise the operation speed of a vertical FET, and a method of fabricating the device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the invention, a semiconductor device is provided, which comprises:
(a) a semiconductor substrate;
(b) a first semiconductor layer of a first conductivity type formed on the substrate,
the first semiconductor layer serving as a first source/drain region;
(c) a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;
the second semiconductor layer having a trench penetrating the same;
(d) a gate electrode formed in the trench by way of a gate dielectric;
the gate electrode having a connection portion located in the trench;
(e) a second source/drain region of the first conductivity type formed in a surface area of the second semiconductor layer;
(f) an interlayer dielectric layer formed on the second semiconductor layer to cover the gate electrode;
the interlayer dielectric layer having a contact hole that exposes the connection portion of the gate electrode;
(g) a conductive plug filled in the contact hole in such a way as to contact the connection portion of the gate electrode; and
(h) a wiring layer formed on the interlayer dielectric layer in such a way as to contact the plug;
the wiring layer being electrically connected to the connection portion of the gate electrode by way of the plug.
With the semiconductor device according to the first aspect of the invention, the gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the contact hole that exposes the connection portion of the gate electrode, where the connection portion is located in the trench. The conductive plug is filled in the contact hole of the interlayer dielectric layer in such a way as to contact the connection portion of the gate electrode. The wiring layer is formed on the interlayer dielectric layer in such a way as to contact the plug, resulting in the wiring layer being electrically connected to the connection portion of the gate electrode by way of the plug.
Accordingly, unlike the previously-explained prior-art semiconductor device 100 of FIGS. 1A and 1B, there is no need to form a connection portion for the gate electrode outside the trench. This means that the gate dielectric does not include a weak or thinner portion where dielectric breakdown is likely to occur. As a result, dielectric breakdown of the gate dielectric is prevented or effectively suppressed, which improves or raises the gate withstand voltage of a vertical FET.
Moreover, unlike the prior-art device 100 of FIGS. 1A and 1B, there is no need to conduct high-temperature treatment for the purpose of raising the gate withstand voltage of a vertical FET. Therefore, vertical FET can be easily formed to have a shallow structure, which means that the parasitic capacitance is effectively reduced as desired. As a result, the operation speed of a vertical FET can be raised.
In a preferred embodiment of the device according to the first aspect, an active region is formed or defined on the substrate. The second source/drain region is located in the active region. The wiring layer is located to overlap with a periphery of the active region.
In another preferred embodiment of the device according to the first aspect, the trench is formed to have a lattice-like shape. The second semiconductor layer is divided into parts by the trench. The parts of the second semiconductor layer are used to form a plurality of vertical FETs on the substrate.
According to a second aspect of the invention, another semiconductor device is provided, which comprises:
(a) a semiconductor substrate;
(b) a first semiconductor layer of a first conductivity type formed on the substrate;
the first semiconductor layer serving as a first source/drain region;
(c) a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;
the second semiconductor layer having a trench penetrating the same;
(d) a gate electrode formed in the trench by way of a gate dielectric;
the gate electrode having a connection portion located in the trench;
(e) a second source/drain region of the first conductivity type formed in a surface area of the second semiconductor layer;
(f) an interlayer dielectric layer formed on the second semiconductor layer to cover the second source/drain region and the gate electrode;
the interlayer dielectric layer having a first contact hole that exposes the connection portion of the gate electrode and a second contact hole that exposes the second source/drain region;
(g) a first conductive plug filled in the first contact hole in such a way as to contact the connection portion of the gate electrode;
(h) a second conductive plug filled in the second contact hole in such a way as to contact the second source/drain region;
(i) a first wiring layer formed on the interlayer dielectric layer in such a way as to contact the first plug;
the first wiring layer being electrically connected to the connection portion of the gate electrode by way of the first plug; and
(j) a second wiring layer formed on the interlayer dielectric layer in such a way as to contact the second plug;
the second wiring layer being electrically connected to the source region by way of the second plug.
With the semiconductor device according to the second aspect of the invention, the gate electrode is formed in the trench of the second semiconductor layer. The interlayer dielectric layer has the first contact hole that exposes the connection portion of the gate electrode and the second contact hole that exposes the second source/drain region, where the connection portion is located in the trench. The first conductive plug is filled in the first contact hole in such a way as to contact the connection portion of the gate electrode. The second conductive plug is filled in the second contact hole in such a way as to contact the second source/drain region. The first wiring layer is formed on the interlayer dielectric layer in such a way as to contact the first plug, resulting in the first wiring layer being electrically connected to the connection portion of the gate electrode by way of the first plug. The second wiring layer is formed on the interlayer dielectric layer in such a way as to contact the second plug, resulting in the second wiring layer being electrically connected to the source region by way of the second plug,
Accordingly, like the device according to the first aspect, there is no need to form a connection portion for the gate electrode outside of the trench. This means that the gate dielectric does not include a weak or thinner portion where dielectric breakdown is likely to occur. As a result, dielectric breakdown of the gate dielectric is prevented or effectively suppressed, which improves the gate withstand voltage of a vertical FET.
Moreover, like the device according to the first aspect, there is no need to conduct high-temperature treatment for the purpose of raising the gate withstand voltage of a vertical FET. Therefore, a vertical FET can be easily formed to have a shallow structure. This means that the parasitic capacitance is effectively reduced as desired. As a result, the operation speed of a vertical FET can be raised.
In addition, with the previously-explained prior-art semiconductor device 100 of FIGS. 1A and 1B, to electrically connect the source wiring layer to the source region, the source wiring layer needs to fill a corresponding contact hole. Thus, the contact hole for the source wiring layer is difficult to be miniaturized, which results in a problem that miniaturization of a vertical FET is difficult.
On the other hand, with the semiconductor device of the second aspect, the second wiring layer (e.g., the source wiring layer) is electrically connected to the second source/drain region by way of the second conductive plug. Thus, the second contact hole for the source wiring layer can be miniaturized, which results in miniaturization of a vertical FET.
In a preferred embodiment of the device according to the second aspect, an active region is formed on the substrate. The second source/drain region is located in the active region. The first wiring layer is located to overlap with a periphery of the active region.
In another preferred embodiment of the device according to the second aspect, the trench is formed to have a lattice-like shape. The second semiconductor layer is divided into parts by the trench. The parts of the second semiconductor layer are used to form a plurality of vertical FETs on the substrate.
In still another preferred embodiment of the device according to the second aspect, each of the first contact hole and the second contact hole has a size approximately equal to a width of the trench. There is an additional advantage that both of the first and second contact holes can be designed according to the same design rule.
According to a third aspect of the invention, a method of fabricating the semiconductor device according to the first aspect is provided. This method comprises:
(a) forming a first semiconductor layer of a first conductivity type on a semiconductor substrate;
the first semiconductor layer serving as a first source/drain region;
(b) forming a second semiconductor layer of a second conductivity type on the first semiconductor layer;
(c) forming a trench in the second semiconductor layer in such a way that the trench penetrates the second semiconductor layer;
(d) forming a gate electrode in the trench by way of a gate dielectric;
the gate electrode having a connection portion located in the trench;
(e) forming a second source/drain region of the first conductivity type in a surface area of the second semiconductor layer;
(f) forming an interlayer dielectric layer on the second semiconductor layer to cover the gate electrode;
(g) selectively removing the interlayer dielectric layer to form a contact hole that exposes the connection portion of the gate electrode;
(h) forming a conductive plug to fill the contact hole in such a way as to contact the connection portion of the gate electrode; and
(i) forming a wiring layer on the interlayer dielectric layer in such a way as to contact the plug;
the wiring layer being electrically connected to the connection portion of the gate electrode by way of the plug.
With the method according to the third aspect, it is obvious that the semiconductor device of the first aspect is fabricated.
In a preferred embodiment of the method according to the third aspect, a step of forming an active region on the substrate is additionally provided. The second source/drain region is located in the active region. The wiring layer is located to overlap with a periphery of the active region.
In another preferred embodiment of the method according to the third aspect, the trench is formed to have a lattice-like shape in the step (c). The second semiconductor layer is divided into parts by the trench. The parts of the second semiconductor layer are used to form a plurality of vertical FETs on the substrate.
According to a fourth aspect of the invention, a method of fabricating the semiconductor device according to the second aspect is provided. This method comprises:
(a) forming a first semiconductor layer of a first conductivity type on a semiconductor substrate;
the first semiconductor layer serving as a first source/drain region;
(b) forming a second semiconductor layer of a second conductivity type on the first semiconductor layer;
(c) forming a trench in the second semiconductor layer in such a way that the trench penetrates the second semiconductor layer;
(d) forming a gate electrode in the trench by way of a gate dielectric;
the gate electrode having a connection portion located in the trench;
(e) forming a second source/drain region of the first conductivity type in a surface area of the second semiconductor layer;
(f) forming an interlayer dielectric layer on the second semiconductor layer to cover the gate electrode;
(g) selectively removing the interlayer dielectric layer to form a first contact hole that exposes the connection portion of the gate electrode and a second contact hole that exposes the second source/drain region;
(h) forming a first conductive plug to fill the first contact hole in such a way as to contact the connection portion of the gate electrode and a second conductive plug to fill the second contact hole in such a way as to contact the second source/drain region; and
(i) forming a first wiring layer and a second wiring layer on the interlayer dielectric layer in such a way as to contact the first plug and the second plug, respectively;
the first wiring layer being electrically connected to the connection portion of the gate electrode by way of the first plug;
the second wiring layer being electrically connected to the second source/drain region by way of the second plug.
With the method according to the fourth aspect, it is obvious that the semiconductor device of the second aspect is fabricated.
In a preferred embodiment of the method according to the fourth aspect, a step of forming an active region on the substrate is additionally provided. The second source/drain is located in the active region. The wiring layer is located to overlap with a periphery of the active region.
In another preferred embodiment of the method according to the fourth aspect, the trench is formed to have a lattice-like shape in the step (c). The second semiconductor layer is divided into parts by the trench. The parts of the second semiconductor layer are used to form a plurality of vertical FETs on the substrate.
In still another preferred embodiment of the method according to the fourth aspect, each of the first contact hole and the second contact hole is formed to have a size approximately equal to a width of the trench in the step (g). There is an additional advantage that both of the first and second contact holes can be designed according to the same design rule.